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advance product information this document contains information for a new product. cirrus logic reserves the right to modify this product without notice. 1 copyright ? cirrus logic, inc. 2000 (all rights reserved) p.o. box 17847, austin, texas 78760 (512) 445 7222 fax: (512) 445 7581 http://www.cirrus.com features l 24-bit conversion l supports 96 khz sample rates l 98 db dynamic range at 3 v supply l -88 dbfs thd+n l 1.8 to 3.3 volt supply l 16-pin tssop package l low power consumption C 11 mw at 1.8 v l internal high pass filter to remove dc offsets l linear phase digital anti-alias filter description the cs5333 is a highly integrated, 24-bit, 96 khz audio adc providing stereo analog-to-digital converters using delta-sigma conversion techniques. this device includes line level inputs in a 16-pin tssop package. the cs5333 is based on delta-sigma modulation allow- ing infinite adjustment of the sample rate between 2 khz and 100 khz simply by changing the master clock frequency. the cs5333 operates from a +1.8 v to +3.3 v supply. these features are ideal for set-top boxes, a/v receiv- ers, dvd-karaoke players or any system which requires optimal performance in a minimum of space. ordering information cs5333-kz -10 to 70 c 16-pin tssop CDB5333 evaluation board i i mclk gnd vq filt+ ref_gnd s/h s/h comparator comparator dac dac lp filter lp filter + - + - + - + - ainr ainl digital decimation filter digital decimation filter hpf hpf serial port sdata lrck sclk vl rst va div dif tst cs5333 24-bit, 96 khz stereo a/d converter dec 00 ds520pp1
cs5333 2 ds520pp1 table of contents 1. characteristics/specifications ................................................................................. 4 analog characteristics ................................................................................................ 4 analog characteristics ................................................................................................ 5 power and thermal characteristics....................................................................... 6 digital characteristics ................................................................................................. 7 absolute maximum ratings ........................................................................................... 7 recommended operating conditions ....................................................................... 7 switching characteristics .......................................................................................... 8 2. typical connection diagram .................................................................................... 10 3. pin description ......................................................................................................... ...... 11 4. applications .............................................................................................................. ........ 13 4.1 grounding and power supply decoupling ....................................................................... 13 4.2 oversampling modes ....................................................................................................... 1 3 4.3 recommended power-up sequence ............................................................................... 13 4.4 master/slave mode ......................................................................................................... .13 5. parameter definitions .................................................................................................. 17 6. references ................................................................................................................ ........ 17 7. package dimensions ....................................................................................................... 1 8 contacting cirrus logic support for a complete listing of direct sales, distributor, and sales representative contacts, visit the cirrus logic web site at: http://www.cirrus.com/corporate/contacts/sales.cfm preliminary product information describes products which are in production, but for which full characterization data is not yet available. advance product infor- mation describes products which are in development and subject to development changes. cirrus logic, inc. has made best effort s to ensure that the information contained in this document is accurate and reliable. however, the information is subject to change without notice and is provi d ed as is without warranty of any kind (express or implied). customers are advised to obtain the latest version of relevant information to verify, before pla cing orders, that information being relied on is current and complete. all products are sold subject to the terms and conditions of sale supplied at the time of o rder acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. no responsibility is assumed by cirrus logic, inc. f or the use of this information, including use of this information as the basis for manufacture or sale of any items, nor for infringements of patents or other rights of third parties. this document is the property of cirrus logic, inc. and by furnishing this information, cirrus logic, inc. grants no license, express or implied un der any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights of cirrus logic, inc. cirrus logic, inc., copyrigh t owner of the information contained herein, gives consent for copies to be made of the information only for use within your organization with respect to cirrus log ic integrated circuits or other parts of cirrus logic, inc. the same consent is given for similar information contained on any cirrus logic website or disk. this c onsent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. the names of products of cirrus logic, inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners wh ich may be registered in some jurisdictions. a list of cirrus logic, inc. trademarks and service marks can be found at http://www.cirrus.com .
cs5333 ds520pp1 3 list of figures figure 1. sclk to lrck and sdata, slave mode ........................................................................ 9 figure 2. sclk to lrck and sdata, master mode ...................................................................... 9 figure 3. typical connection diagram.......................................................................................... 1 0 figure 4. base-rate stopband rejection...................................................................................... 14 figure 5. base-rate transition band............................................................................................ 14 figure 6. base-rate transition band (detail) ............................................................................... 14 figure 7. base-rate passband ripple.......................................................................................... 14 figure 8. high-rate stopband rejection ...................................................................................... 14 figure 9. high-rate transition band............................................................................................ .14 figure 10. high-rate transition band (detail) .............................................................................. 15 figure 11. high-rate passband ripple......................................................................................... 15 figure 12. line input test circuit ............................................................................................. ..... 15 figure 13. cs5333 - serial audio format 0 .................................................................................. 16 figure 14. cs5333 - serial audio format 1 .................................................................................. 16 list of tables table 1. common clock frequencies........................................................................................... 11 table 2. digital interface format - dif........................................................................................ .. 12
cs5333 4 ds520pp1 1. characteristics/specifications analog characteristics (t a = 25 c; gnd = 0 v logic "1" = vl = 1.8 v; logic "0" = gnd = 0 v; mclk = 12.288 mhz; fs for base-rate mode = 48 khz, sclk = 3.072 mhz, measurement bandwidth 10 hz to 20 khz, unless otherwise specified; fs for high-rate mode = 96 khz, sclk = 6.144 mhz, measurement bandwidth 10 hz to 20 khz, unless otherwise specified.) notes: 1. referenced to typical full-scale differential input voltage. parameter symbol base-rate mode high-rate mode unit min typ max min typ max analog input characteristics for va = 1.8 v dynamic range a-weighted unweighted tbd tbd 91 88 - - tbd tbd 94 91 - - db db total harmonic distortion + noise (note 1) -1 db -20 db -60 db thd+n - - - -88 -68 -28 tbd - - - - - -88 -68 -31 tbd - - db db db analog input characteristics for va = 3.0 v dynamic range a-weighted unweighted tbd tbd 96 93 - - tbd tbd 98 95 - - db db total harmonic distortion + noise (note 1) -1 db -20 db -60 db thd+n - - - -88 -68 -33 tbd - - - - - -85 -65 -35 tbd - - db db db analog input characteristics for va = 1.8 or 3.0 v interchannel isolation 1 khz - 90 - - 90 - db interchannel gain mismatch - 0.1 - - 0.1 - db offset error with high pass filter - - 0 - - 0 lsb full scale input voltage tbd va3.6 tbd tbd va3.6 tbd vrms voltage common mode va2 va2 v gain drift - 100 - - 100 - ppm/c input resistance 10 - - 10 - - k w input capacitance - - 15 - - 15 pf
cs5333 ds520pp1 5 analog characteristics (continued) notes: 2. filter response is guaranteed by design. 3. filter characteristics scale with output sample rate. for output sample rates, fs, other than 48 khz, the 0.01 db passband edge is 0.4535x fs and the stopband edge is 0.625x fs. 4. the analog modulator samples the input at 6.144 mhz for an fs equal to 48 khz. there is no rejection of input signals which are multiples of the sampling frequency (n x 6.144 mhz 21.8 khz where n = 0,1,2,3...). 5. group delay for fs = 48 khz, t gd = 15/48 khz = 312 s. parameter symbol base-rate mode high-rate mode unit min typ max min typ max a/d decimation filter characteristics (note 2) passband (note 3) 0 - 23.5 0 - 47.5 khz passband ripple -0.08 - +0.17 -0.09 - 0 db stopband (note 3) 27.5 - - 64.1 - - khz stopband attenuation (note 4) -60.3 - - -48.4 - - db group delay (fs = output sample rate) (note 5) t gd - 10/fs - - 2.7/fs - s group delay variation vs. frequency d t gd - - 0.03 - - 0.007 s high pass filter characteristics frequency response -3 db (note 3) -0.1 db - - 3.7 24.2 - - - - 3.7 24.2 - - hz hz phase deviation @ 20 hz (note 3) - 10 - - 10 - degree passband ripple (note 2) - - 0.17 - - 0.09 db
cs5333 6 ds520pp1 power and thermal characteristics notes: 6. valid with the recommended capacitor values on filt+ and vq as shown in figure 3. 7. power down mode is defined as reset active with mclk being applied. to lower power consumption further, remove mclk. base-rate mode high-rate mode parameters symbol min typ max min typ max units power supplies power supply current- va=1.8 v normal operation vl=1.8 v i a i d_io - - 6.0 150 - - - - 7.6 300 - - ma a power supply current- va=1.8 v power down mode (note 7) vl=1.8 v i a i d_io - - 100 0 - - - - 250 0 - - a a power supply current- va=3.0 v normal operation vl=3.0 v i a i d_io - - 9 260 - - - - 11.5 520 - - ma a power supply current- va=3.0 v power down mode vl=3.0 v i a i d_io - - 250 0 - - - - 500 0 - - a a total power dissipation- all supplies=1.8 v normal operation all supplies=3.0 v - - 11 28 tbd tbd - - 14.5 36 tbd tbd mw mw package thermal resistance q ja -75- -75-c/watt power supply rejection ratio (1 khz) (note 6) (60 hz) psrr - - 60 40 - - - - 60 40 - - db db
cs5333 ds520pp1 7 digital characteristics (t a = 25 c; vl = 1.7 v - 3.6 v; gnd = 0 v) absolute maximum ratings (gnd = 0 v; all voltages with respect to ground.) warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. recommended operating conditions (gnd = 0 v; all voltages with respect to ground.) parameters symbol min typ max units high-level input voltage v ih 0.7?vl - - v low-level input voltage v il - - 0.3?vl v high-level output voltage v oh 0.7?vl - - v low-level output voltage v ol - - 0.3?vl v leakage current i in --10 m a input capacitance - 8 - pf parameters symbol min max units dc power supplies: positive analog digital i/o va vl -0.3 -0.3 4.0 4.0 v v input current, any pin except supplies i in -10ma digital input voltage v ind -0.3 vl+0.4 v ambient operating temperature (power applied) t a -55 125 c storage temperature t stg -65 150 c parameters symbol min typ max units ambient temperature t a -10 - 70 c dc power supplies: positive analog digital i/o va vl 1.7 1.7 - - 3.6 3.6 v v
cs5333 8 ds520pp1 switching characteristics (t a = -10 to 70 c; vl = 1.7 v - 3.6 v; inputs: logic 0 = gnd, logic 1 = vl, c l = 20 pf) parameters symbol min typ max units input sample rate base rate mode high rate mode fs fs 2 50 - - 50 100 khz khz mclk pulse width high mclk/lrck = 1024 8 - - ns mclk pulse width low mclk/lrck = 1024 8 - - ns mclk pulse width high mclk/lrck = 768 10 - - ns mclk pulse width low mclk/lrck = 768 10 - - ns mclk pulse width high mclk/lrck = 512 15 - - ns mclk pulse width low mclk/lrck = 512 15 - - ns mclk pulse width high mclk / lrck = 384 or 192 21 - - ns mclk pulse width low mclk / lrck = 384 or 192 21 - - ns mclk pulse width high mclk / lrck = 256 or 128 31 - - ns mclk pulse width low mclk / lrck = 256 or 128 31 - - ns master mode sclk falling to lrck edge t slrd -20 - 20 ns sclk falling to sdata valid t sdo 0 - 20 ns sclk duty cycle 40 50 60 % slave mode lrck duty cycle - 50 - % sclk pulse width low t sclkl 20 - - ns sclk pulse width high t sclkh 20 - - ns sclk period base rate mode high rate mode t sclkw t sclkw - - - - ns ns sclk falling to lrck edge t slrd -20 - 20 ns sclk falling to sdata valid base rate mode high rate mode t dss t dss - - - - ns ns 1 128 () fs --------------------- - 1 64 () fs ------------------ 1 (512)fs 1 (256)fs
cs5333 ds520pp1 9 sclk lrck sdata t sclkl t slrd t dss msb t sclkh t sclkw figure 1. sclk to lrck and sdata, slave mode sclk lrck sdata t slrd t sdo msb msb-1 figure 2. sclk to lrck and sdata, master mode
cs5333 10 ds520pp1 2. typical connection diagram va cs5333 1.8 to 3.3 v supply 1.0 f 0.1 f + 1.8 to 3.3 v supply 1.0 f + vl 5 1 0.47 f 150 w 0.47 f 150 w ainl ainr ** 14 13 0.01 f 0.01 f 0.1 f gnd 6 tst 10 filt+ ref_gnd 1.0 f + 11 12 vq 1.0 f 15 + mclk lrck sclk digital audio source sdata 2 7 3 4 rst dif div mode configuration 16 9 8 47k w connect to: ? vl for master mode ? gnd for slave mode * all capacitors located on the analog input lines should be of the type cog or equivalent. * **optional if analog input circuit is biased within 5% of cs5333 nominal bias voltage ** * * * figure 3. typical connection diagram
cs5333 ds520pp1 11 3. pin description interface power vl rst reset master clock mclk vq quiescent voltage serial clock sclk ainl left channel analog input serial data output sdata ainr right channel analog input analog power va ref_gnd reference ground ground gnd filt+ positive voltage reference left right clock lrck tst test input mclk divide div dif digital interface format 1 2 3 4 5 6 7 8 5 1 2 6 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 5 1 2 6 16 15 14 13 12 11 10 9 sample rate (khz) mclk (mhz) hrm brm 128x 192x 256x* 384x* 256x 384x 512x 768x* 1024x* 32 4.0960 6.1440 8.1920 12.2880 8.1920 12.2880 16.3840 24.5760 32.7680 44.1 5.6448 8.4672 11.2896 16.9344 11.2896 16.9344 22.5792 32.7680 45.1584 48 6.1440 9.2160 12.2880 18.4320 12.2880 18.4320 24.5760 36.8640 49.1520 64 8.1920 12.2880 16.3840 24.5760 - - - - - 88.2 11.2896 16.9344 22.5792 33.8688 - - - - - 96 12.2880 18.4320 24.5760 36.8640 - - - - - * div= hi table 1. common clock frequencies interface power 1 vl ( input ) - digital interface power supply. typically 1.8 to 3.3 vdc. master clock 2 mclk ( input ) - the master clock frequency must be either 256x, 384x, 512x, 768x or 1024x the input sample rate in base rate mode (brm) and 128x, 192x, 256x, 384x the input sample rate in high rate mode (hrm). table 1 illustrates several standard audio sample rates and the required master clock frequencies. serial clock 3 sclk ( input / output ) - clocks the individual bits of the serial data out of the sdout pin. the required relationship between the left/right clock, serial clock and serial data is defined by the dif pin. serial audio data out (m/s select) 4 sdata ( output ) - this pin serves two functions. first: two's complement msb-first serial data is output on this pin. the data is clocked out of sdout via the serial clock and the channel is determined by the left/right clock. the required relationship between the left/right clock, serial clock and serial data is defined by the dif pin. second: master/slave mode selection is determined, at startup, by a 47 kohm pullup/pull- down on this line. a pullup to vl selects master mode and a pulldown to gnd selects slave mode. analog power 5 va ( input ) - analog power supply. typically 1.8 to 3.3 vdc. ground 6 gnd ( input ) - ground reference.
cs5333 12 ds520pp1 left/right clock 7 lrck ( input / output ) - the left/right clock determines which channel is currently being output on the serial audio data line sdout. the frequency of the left/right clock must be at the input sample rate. the required relationship between the left/right clock, serial clock and serial data is defined by the dif pin. mclk divide enable 8 div ( input ) - this pin serves different functions in master and slave modes. in master mode: when high, the chip will enter high rate mode; when this pin is low, the chip will enter base rate mode. in slave mode: when high, mclk is divided internally by 2; when low, mclk is not changed. digital interface format 9 dif ( input ) - the required relationship between the left/right clock, serial clock and serial data is defined by the digital interface format. test input 10 tst ( input ) - must be connected directly to ground. positive voltage reference 11 filt+ ( output) - positive reference for internal sampling circuits. an external capacitor is required from filt+ to ground, as shown in figure 3. the recommended value will typi- cally provide 60 db of psrr at 1 khz and 40 db of psrr at 60 hz. filt+ is not intended to supply external current. filt+ has a typical source impedance of 250 k w and any cur- rent drawn from this pin will alter device performance. reference ground 12 ref_gnd ( input ) - ground reference for the internal sampling circuits. must be con- nected to ground. analog inputs 13,14 ainr, ainl ( input ) - the full scale analog input level is specified in the analog character- istics specification table. quiescent voltage 15 vq ( output ) - filter connection for internal a/d converter quiescent reference voltage. a capacitor must be connected from vq to ground. vq is not intended to supply external current. vq has a typical source impedance of 250 k w and any current drawn from this pin will alter device performance. reset 16 rst ( input ) - when low the device enters a low power mode and the part is in reset. when high, the part returns to normal operation within 1024 lrck cycles. dif description 0 i 2 s, up to 24-bit data 1 left justified, up to 24-bit data table 2. digital interface format - dif
cs5333 ds520pp1 13 4. applications 4.1 grounding and power supply decoupling as with any high resolution converter, the cs5333 requires careful attention to power supply and grounding arrangements to optimize performance. figure 3 show the recommended power arrange- ment with va and vl connected to clean supplies. decoupling capacitors should be located as close to the device package as possible. 4.2 oversampling modes the cs5333 operates in one of two oversampling modes. base rate mode supports input sample rates up to 50 khz while high rate mode supports input sample rates up to 100 khz. see table 1 for more details. 4.3 recommended power-up sequence 1) hold rst low until the power supply, master, and left/right clocks are stable. in this state, vq will remain low. 2) bring rst high. the device will remain in a low power state with vq low and will initiate the power-up sequence. this power-up se- quence takes approximately 1024 lrck cycles to complete. 4.4 master/slave mode in master, base rate mode (pull-up on sdata, div=0), the cs5333 requires a 256x mclk and provide a 64x sclk. in master, high rate mode (pull-up on sdata, div=1), the cs5333 requires a 128x mclk and provide a 64x sclk. the vari- ous clocking ratios required in slave mode (pull- down on sdata) are listed under the description of mclk, on page 11.
cs5333 14 ds520pp1 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 frequency (normalized to fs) amplitude db -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.4 0.42 0. 44 0.46 0. 48 0. 5 0. 52 0.54 0. 56 0. 58 0. 6 frequency (normalized to fs) amplitude db figure 4. base-rate stopband rejection figure 5. base-rate transition band -0.3 -0.25 -0.2 -0.15 -0.1 -0.05 0 0. 05 0.1 0. 15 0.2 0. 25 0.3 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 frequency (normalized to fs) amplitude db figure 6. base-rate transition band (detail) figure 7. base-rate passband ripple -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 0. 45 0. 46 0. 47 0. 48 0.49 0.5 0. 51 0. 52 0. 53 0. 54 0. 55 frequency (normalized to fs) amplitude db -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 frequency (normalized to fs) amplitude db -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.4 0.43 0.46 0.49 0.52 0.55 0.58 0.61 0.64 0.67 frequency (normalized to fs) amplitude db figure 8. high-rate stopband rejection figure 9. high-rate transition band
cs5333 ds520pp1 15 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55 frequency (normalized to fs) amplitude db -0.3 -0.25 -0.2 -0.15 -0.1 -0.05 0 0.05 0.1 0.15 0.2 0.25 0.3 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 frequency (normalized to fs) amplitude db figure 10. high-rate transition band (detail) figure 11. high-rate passband ripple gnd ainx 150 w 0.47 f 0.01 f figure 12. line input test circuit
cs5333 16 ds520pp1 lrck sclk left channel right channel sdata +3 +2 +1 lsb +5 +4 msb -1 -2 -3 -4 -5 +3 +2 +1 lsb +5 +4 msb -1 -2 -3 -4 i 2 s, up to 24-bit data. data valid on rising edge of sclk figure 13. cs5333 - serial audio format 0 lrck sclk left channel right channel sdata +3 +2 +1 lsb +5 +4 msb -1 -2 -3 -4 -5 +3 +2 +1 lsb +5 +4 msb -1 -2 -3 -4 left justified, up to 24-bit data. data valid on rising edge of sclk. figure 14. cs5333 - serial audio format 1
cs5333 ds520pp1 17 5. parameter definitions total harmonic distortion + noise (thd+n) the ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10 hz to 20 khz), including distortion components. expressed in decibels. dynamic range the ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. dynamic range is a signal-to-noise measurement over the specified bandwidth made with a -60 dbfs signal. 60 db is then added to the resulting measurement to refer the measurement to full scale. this technique ensures that the distortion components are below the noise level and do not effect the measurement. this measurement technique has been accepted by the audio engineering so- ciety, aes17-1991, and the electronic industries association of japan, eiaj cp-307. interchannel isolation a measure of crosstalk between the left and right channels. measured for each channel at the converter's output with all zeros to the input under test and a full-scale signal applied to the other channel. units in decibels. interchannel gain mismatch the gain difference between left and right channels. units in decibels. gain error the deviation from the nominal full scale analog output for a full scale digital input. gain drift the change in gain value with temperature. units in ppm/c. 6. references 1. "how to achieve optimum performance from delta-sigma a/d & d/a converters" by steven harris. paper presented at the 93rd convention of the audio engineering society, october 1992. 2. CDB5333 evaluation board datasheet.
cs5333 18 ds520pp1 7. package dimensions notes: 1. d and e1 are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. dimension b does not include dambar protrusion/intrusion. allowable dambar protrusion shall be 0.13 mm total in excess of b dimension at maximum material condition. dambar intrusion shall not reduce dimension b by more than 0.07 mm at least material condition. 3. these dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips inches millimeters note dim min nom max min nom max a -- -- 0.043 -- -- 1.10 a1 0.002 0.004 0.006 0.05 -- 0.15 a2 0.03346 0.0354 0.037 0.85 0.90 0.95 b 0.00748 0.0096 0.012 0.19 0.245 0.30 2,3 d 0.193 0.1969 0.201 4.90 5.00 5.10 1 e 0.248 0.2519 0.256 6.30 6.40 6.50 e1 0.169 0.1732 0.177 4.30 4.40 4.50 1 e -- 0.026 bsc -- -- 0.065 bsc -- l 0.020 0.024 0.028 0.50 0.60 0.70 0 4 8 0 4 8 jedec #: mo-153 controlling dimension is millimeters 16l tssop (4.4 mm body) package drawing e n 1 23 e b 2 a1 a2 a d seating plane e1 1 l side view end view top view
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